1. Field of the Invention
The present invention relates to a digital control pulse generator which allows control of a pulse generating cycle by digital data and which is applicable to a digital control oscillator which, for example, allows control of its oscillation cycle by digital data.
2. Description of Related Art
Conventionally a voltage controlled oscillator (known as a VCO) which allows control of an oscillation frequency thereof by an analog control voltage is used as a frequency variable oscillator in a PLL (Phase Locked Loop) of communication equipment, motor controlling equipment and other types of equipment.
However, because such a VCO requires particular resistors and capacitors to obtain a necessary central oscillation frequency, it has such problems that such resistors and capacitors have to be replaced in changing the central oscillation frequency, that a fine adjustment of the resistors and capacitors has to be made in order to maintain its accuracy (its controllability is not good), and that its power consumption is large because it uses an analog circuit.
In view of this, in Japanese Publication No. JP-A-5-102801 (Watanabe U.S. application Ser. No. 956,955), the applicant of the present invention has proposed a digital control oscillator comprising a pulse circulating circuit composed of an odd number of inversion circuits linked in a ring, for circulating a pulse signal, a switching circuit for increasing/decreasing the number of linked stages of the inversion circuits composing the pulse circulating circuit by even numbers of stages according to digital data from the outside, an output terminal for taking out the pulse signal circulating within the pulse circulating circuit, a counter for counting the pulse signal circulating within the pulse circulating circuit to detect that the pulse signal has circulated a number of times specified by the digital data from the outside and an output circuit for outputting a predetermined output signal at a timing wherein the pulse signal from the output terminal is inverted when the counter detects that the pulse signal has circulated by the number of times specified by the digital data from the outside.
In the apparatus proposed in Japanese Laid-Open Patent No. 5-102801, the period of time which the pulse signal requires to circulate the pulse circulating circuit once (pulse circulating time) T (T=x * Td) is determined by the number of linked stages of the inversion circuits composing the pulse circulating circuit and the inversion operating time Td of each inversion circuit, and the cycle by which the output signal is output from the output circuit, i.e. oscillation cycle HT (HT=x * Td * N), is determined by the pulse circulating time T and the count N of the pulse signal counted by the counter.
Accordingly, the apparatus proposed above allows an oscillation output of a desired cycle to be obtained easily by changing the number of linked stages x of the inversion circuits composing the pulse circulating circuit and the count value N of the counter respectively by digital data.
Further, if the number of stages of the inversion circuits for circulating the pulse signal is switched during the time when the pulse signal circulates within the pulse circulating circuit by setting the number of linked stages of the inversion circuits at x1 only when the pulse signal circulates the pulse circulating circuit in the first time and by setting the number of linked stages of the inversion circuits at x2 which is less than x1 during the time when the pulse circulates on and after the second time in digitally controlling the oscillation cycle, the apparatus proposed above is known to allow control of the oscillation cycle in detail by coarsely determining it by the count value N of the counter and then by finely adjusting it by the value of x1 because the oscillation cycle is Td * (x1+x2 * (N-1)).
Further, as such a digital control oscillator, one comprising a pulse circulating circuit composed of an odd number of inversion circuits linked in a ring, a counter for counting a pulse signal circulating within the pulse circulating circuit and for outputting a predetermined output signal when its count value reached a value specified by digital data from the outside, a delay circuit composed of a plurality of inversion circuits which temporarily stop the pulse circulating operation in the pulse circulating circuit when the output signal is output from the counter and starts the pulse circulating circuit again when a predetermined delay time has elapsed and a switching circuit for increasing/decreasing the number of linked stages of the inversion circuits within the delay circuit have been proposed as disclosed in U.S. Pat. No. 5,045,811.
The apparatus disclosed in U.S. Pat. No. 5,045,811 allows the output signal from the counter to be used as an oscillation output and its oscillation cycle is equal to a period of time in which a period of time determined by multiplying the pulse circulating time determined by the number of linked stages x3 of the inversion circuits composing the pulse circulating circuit and by the inversion operating time Td of each inversion circuit (x3 * Td) with the count N of the counter (x3 * Td * N) and a delay time (x4 * Td) determined by the number of linked stages x4 of the inversion circuits composing the delay circuit and the inversion operating time Td of each inversion circuit, i.e. Td * (x3 * N+x4) are added. Accordingly, this apparatus allows the oscillation cycle to be determined coarsely by the count N of the counter and allows it to be finely adjusted by setting the number of linked stages x4 of the inversion circuits composing the delay circuit.
However, the apparatus disclosed in Japanese Laid-Open Patent No. 5-102801 which the applicant of the present invention has proposed has the following problems.
That is, while the number of stages of the inversion circuits is changed, for example from x1 to x2 which is smaller than x1 during the time when the pulse signal circulates in the pulse circulating circuit as described above to digitally control the oscillation cycle in more detail in the apparatus described above, the number of linked stages of the inversion circuits has to be changed from x2 to x1 which conversely is larger than x2 when the output signal is output from the output circuit, i.e., when one cycle of the oscillation cycle passes.
However, because the input/output level of each inversion circuit to be increased cannot be predicted when the number of linked stages of the inversion circuits is increased, the pulse signal can be circulated only after stabilizing the pulse circulating circuit by extinguishing the pulse signal within the pulse circulating circuit once. Therefore, the operation of the pulse circulating circuit is forcibly stopped for a predetermined period of time per each cycle of the oscillation output and the pulse circulating circuit is operated again after completely extinguishing the pulse signal in the apparatus proposed in Japanese Patent Laid-Open No. 5-102801.
Because the stop and start of the pulse circulating circuit have to be repeated per each cycle of the oscillation cycle in the apparatus described above, the oscillation cycle HT does not become Td * (x1+x2 * (N-1) precisely but becomes a period of time in which a time Ta for temporarily stopping the pulse circulating circuit is added to that value. That is, although the oscillation cycle may be changed corresponding to digital data, the time Ta for temporarily stopping the pulse circulating circuit becomes an offset error in setting the oscillation cycle, making it impossible to set the oscillation cycle in proportion to digital data indicating the number of linked stages of the inversion circuits and the count of the counter. Further, because the pulse circulating circuit has to be temporarily stopped, there is a lower limit in setting the length of the oscillation cycle.
On the other hand, the prior art apparatus disclosed in U.S. Pat. No. 5,045,811 has a problem that because the count N of the counter and the number of linked stages x4 of the inversion circuits in the delay circuit for determining a delay time are independently controlled, the digital data from the outside which indicates an oscillation cycle cannot be used as it is to control the oscillation cycle and the digital data has to be converted once into data respectively indicating the count N and the number of linked stages x4.